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Staff Design Verification Engineer 

adzuna-us  |  United States  |  

United StatesCuster Rd, null, 75023
Information Technology/Computing
Work Type:
Work Time:
Full Time


Job no.004348Position TypeResearch & DevelopmentWorking timeRegular FulltimePlace of employmentPlano, TXWhat we offer:Career PathProfit SharingPerformance IncentivesJob TrainingHealth BenefitsOn-Site GymPension / Insurance BenefitsSocial Events Your tasks and responsibilities

- Responsible for design verification of mixed signal integrated circuits, using both directed tests and constrained random regressions

- Proficiency in System Verilog and UVM including: writing checkers and assertions, customizing constraints, troubleshooting, getting functional coverage collection using cover groups, etc.

- Technical and team leadership – both within the internal project DV team, but also directly supporting customers real time.

- Primary focus is on (digital) design verification, but proficiency with mixed signal design verification and creation / validation of models are a plus

- Creation of test benches and automated verification simulations

- Performing block level and top level design verification

- Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)

- Experience with Formal DV is a plus.Your education and experiences

- Master’s degree in Electrical / Computer Engineering with 5 years of experience in Design Verification, or a Bachelor’s degree with 10 years of experience

- Prefer some experience in a project leadership role

- System Verilog / UVM based DV experience.

Formal DV experience is a plus.

- Collaborative and respectful team player with mentoring skills, and passionate about achieving team goals

- Excellent communication skills (both oral and written) are required, as real time customer level technical interface and design / team leadership is necessary.

- Experience with relevant CAD tools