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Design for Test (DFT) Engineer, Senior Staff 
(Job)

adzuna-us  |  United States  |  

Ref:
ADZUNA-US-ECUQK
Direct:
Employer:
Location:
United StatesE Rosemary Ln, CA, 95008
Category:
Information Technology/Computing
Work Type:
Permanent
Work Time:
Full Time
Tags:
job,united-states,adzuna

Description 

DescriptionThe Design For Test, Staff Engineer will be responsible for the DFT implementation, design, coding, synthesis and static timing analysis of the next general optical networking ASIC.

Typical activities include development of hardware block design specifications, RTL coding, synthesis, formal verification (LEC), static timing analysis and DFT design implementation/ATPG/verification.

The engineer will interface with the backend group for the physical implementation of these hardware blocks.

He or she will also be expected to contribute to development of effective full chip/block DFT methodology.Required Skills & Experience 7 years experience and Bachelor’s in Engineering or equivalent requiredMust be able to develop best in class, highest quality DFT methodologies to meet all test requirements & silicon quality standardsMust drive DFT tools to produces highest quality DFT implementation for both core design as well as integration of IPs.Must drive ATPG tools to meet all silicon coverage requirements.Must work well with RTL design, test engineering teams to implement highest quality DFT implementation.Will have verification responsibilities of chip design for all DFT requirements, including DFT functional verification, DFT coverage verification in all DFT modes.Static Timing/Noise/Coupling Analysis related to all DFT modes or ATPGMust be able to generate clear documentation & easy to use scripts in support DFT flows.Must be capable of driving evaluation of tools in the development of DFT flows.Hands on experience in the following areas:Logic Bist, Memory Bist, Boundary Scan, scan/ATPG design implementation & verificationDFT process/flow development experienceUnderstanding of static timing and crosstalk/noise analysis.Understanding of synthesis/timing closure concepts.Write and read RTL in Verilog and/or VHDL.Coding in scripting languages such as TCL, Perl and UNIX shell.Hands on experience with the following EDA tools:DFT: DFT Compiler/MAX, RTL Compiler, Tessent, TetraMAX, Fastscan, TestKompressLint: Spyglass, NLINTSynthesis: Design Compiler, RTL CompilerStatic timing: Primetime, Tempus indicates the preferred toolsExperience with low power DFT flows highly desirable