Senior/Principal Design-For-Test (DFT) Engineer As part of my clients ongoing expansion, I am looking for a candidate to strengthen the ASIC Implementation team, located in Reading or Cambridge the ideal candidate will have a strong academic record and 5-10 years’ experience in Design for Test (DFT) within digital and mixed-signal ASIC/SoC development.
This role will be located close to Reading, South of the UK and as part of the role the successful engineer will take full-flow ownership of all DFT, MBIST, and test-pattern generation for complex digital and mixed-signal ASIC designs.
They will setup, run, and maintain EDA tool flows relating to DFT, MBIST, and test pattern generation and work closely alongside the Front-end and Back-end teams to implement and verify DFT at all stages in the development flow.
I am looking for a DFT Engineer who will have the following key skills and knowledge; - 1st or 2.1 Electronics, Physics or relevant subject.
- Several years’ experience in industry with a strong track record in DFT gained across several successful ASIC projects, and ideally at process nodes down to and including 16FF - Specific skills in DFT implementation: - Specification at the architecture level - Implementation using tool-based and hand-crafted methods - Integration of IP including CPU’s, Analog Macros, and IO PHYs - MBIST and memory repair integration - Coverage analysis and improvement to meet targets - ATPG, as well as manual and semi-automatic TPG, including simulation-based methods - Implementation of at-speed test methodologies - DFT for power-managed designs - Generation of STA and scenario/mode constraints - Working knowledge of the complete SoC design flow and associated tools and methodologies to deliver working silicon.
- Experience of RTL and gate-level simulation as applied to DFT verification - VHDL/Verilog coding skills For further details and a confidential discussion please contact Rachel Mason IC Resources.